Pearl Semiconductor developed the SpurFree™ PLL architecture to address the growing demand for new timing solutions that achieve better noise performance than currently available state-of-the-art technologies. It is a patented all-digital ultra-low noise PLL architecture enabled by a complex DSP engine. This DSP engine continuously removes "fractional" spurs induced by the traditional sigma-delta fractional-N loop within the PLL. The result is an outstanding spur-free phase noise behavior with an extremely low integrated phase jitter, typically 85 fs spur-inclusive.
SpurFree™ technology maintains its superior noise performance across a wide range of output frequencies, from 0.2 to 3000 MHz. This makes it an ideal timing IC technology for next-generation datacenters connectivity applications. It is the foundation for a family of timing ICs, including programmable reference clocks (XO, VCXO), clock generators, clock buffers, and jitter attenuators.
Pearl Semiconductor’s SpurFree™ PLL architecture delivers exceptional jitter performance, achieving spur-free phase noise with integrated jitter typically as low as 90 fs. This ultra-clean signal quality is enabled by a patented all-digital design and a powerful DSP engine that continuously eliminates fractional spurs within the PLL loop.
When deployed in Pearl’s timing IC products, SpurFree™ technology is combined with advanced temperature-compensation techniques, ensuring frequency stability as tight as ±3 ppm across the full –40 °C to +85 °C range. This makes it a robust platform for high-performance connectivity and datacenter applications, powering reference clocks, clock generators, buffers, and jitter attenuators.
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