A fabless semiconductor company specializing in high performance Reference Clocks and Timing ICs. Our products are based on innovative manufacturing and patented IC design technologies achieving outstanding performance. Pearl Semiconductor aims to be the leading supplier of high performance reference clocks and Timing ICs serving the most demanding industrial, networking, telecom and automotive applications.
Pearl Semiconductor has been developing for the past few years reference clocks and clock generators based on piezoelectric MEMS resonators that are built on top of CMOS. The developed technology allows the introduction of a Single Die reference clock solution that includes the MEMS resonator and required circuitry for oscillation, frequency multiplication and temperature compensation. Pearl used its previous experience and knowledge in MEMS resonator technology to obtain a highly stabilized output and achieve impressive noise performance. The solution allows operation at extended temperature ranges of up to 125°C satisfying needs in Industrial and Automotive applications. The single die solution allows tight thermal coupling between the resonator and temperature sensor resulting in excellent thermal tracking and in turn zero thermal latency. This has allowed fast and economic trimming routines during testing yielding tight frequency stability across the extended temperature ranges. This was not possible without the close collaboration with our manufacturing partner, SilTerra, of the Piezoelectric Monolithic MEMS CMOS Platform. Pearl aims to introduce several families of programmable reference clocks to the market in the near future.
Phase Locked Loops (PLLs) have been used over the years to develop timing solutions ranging from programmable reference clocks and clock generators to jitter attenuators and network synchronizers. Pearl Semiconductor has developed a novel PLL architecture that enjoys all the merits of a Sigma-Delta Fractional-N PLL architecture yet behaves like an integer-N PLL. The result is outstanding spur-free phase noise behavior with unbelievably low integrated phase jitter. This novel PLL architecture uses Pearl’s patented DSP algorithms and circuit techniques to continuously suppress any spurs while minimizing the noise contribution of active circuitry within the PLL bandwidth. Pearl Semiconductor is using this ULN PLL technology to develop Timing solutions serving demanding applications such as OTN modules for 100G/200G/400G/800G, video broadcasting and 5G infrastructure.
CAIRO & AMSTERDAM, MARCH 24, 2021